1. Field of the Invention
The present invention relates generally to techniques to reduce power in a processor which processes instructions having a variety of lengths, and, more particularly, to advantageous techniques for selectively enabling and disabling writing and reading predecode bits in an instruction cache.
2. Relevant Background
Many processors typically support instruction sets having variable length instructions. For example, a processor's instruction set may consist of 32-bit instructions and 16-bit instructions. A processor may also have a hierarchical memory configuration with multi-levels of caches including an instruction cache, a data cache, and system memory. If the processor also has a deep execution pipeline that operates at a high clock rate with short duration pipeline stages, it is also likely that the processor has a predecode stage to preprocess the instructions in order to simplify a subsequent decode stage and, thus, streamline the pipeline. The predecode pipeline stage is commonly operative during an instruction cache miss to partially decode instructions that are fetched due to the instruction miss. The predecode information is written into the instruction cache along with the fetched instructions.
In a variable length instruction processor, the instructions fetched due to a miss may be of varying length. The predecode operation determines a set of predecode bits for each instruction and the instruction and predecode bits are stored in the instruction cache independent of the processor's operating state. The writing and reading of predecode bits which may be unnecessary due to the processor's operating state is a source of power loss.